1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a plurality of chips sealed in a package.
2. Description of the Prior Art
The storage capacity of semiconductor storage devices increases by a factor of four times every three years. The storage capacity obtainable in a generation depends on the level of the lithographic technology achieved in the generation. Recently, it has been required to provide compact, less-expensive, advanced information processing devices. These devices need an increased storage capacity.
In order to increase the storage capacity of the above devices, a semiconductor device has been proposed in which a plurality of chips are sealed in a package (see WO 91/14282). Conventionally, chips of two different types having a mirror symmetry relationship must be provided. Hence, it is not easy to efficiently produce the semiconductor devices having the packaged chips.
FIGS. 1A, 1B and 1C show a conventional semiconductor device having a plurality of chips. The semiconductor device shown in FIGS. 1A, 1B and 1C includes two chips 10 and 12. The chip 10 has a main surface 10a on which circuit elements are arranged, and a back surface 10b. Similarly, the chip 12 has a main surface 12a on which circuit elements are arranged, and a back surface 12b. The chips 10 and 12 are joined together so that the back surfaces 10b and 12b are in contact with each other, and are sealed in a single package 14. The chips 10 and 12 have circuit arrangements having the mirror symmetry relationship. A mark 16 indicates one of two types of circuit arrangements, and a mark 18 indicates the other circuit arrangement type.
Bumps or pads D1-D6 and D8-D12 are provided on the chip 10, and are connected to pins P1-P6 and P8-P12 by leads (bonding, for example) R1-R6 and R8-R12, respectively. Bumps or pads D1'-D6' and D8'-D12' are provided on the chip 12, and are connected to pins P1'-P6' and P8'-P12' by leads (bonding, for example) R1'-R6' and R8'-R12', respectively. Pin P7 are non-connecting pins which are not connected to the chips 10 and 12. Pins P13 and P14 are chip select pins connected to a bump or a pad D13 of the chip 10 and a bump D14' of the chip 12 by leads R13 and R14', respectively.
The pins P1-P6 and P8-P12 other than the pins P13 and P14 are respectively connected to the bumps D1-D6 and D8-D12 formed on the chip 10 and are further connected to the bumps D1'-D6' and D8'-D12', respectively. The semiconductor device shown in FIGS. 1A-1C has a storage capacity approximately equal to twice the storage capacity of the conventional semiconductor device having a package size equal to that of the conventional semiconductor device.
The semiconductor device shown in FIGS. 1A-1C uses the two different types of chips. That is, the two different circuit arrangements having the mirror symmetry relationship are used. Hence, two different mask patterns must be prepared though the sequences of the production steps for the chips 10 and 12 of the different types are the same as each other. It follows that the semiconductor device cannot be efficiently produced and that a very complex production line is needed. Further, it is troublesome to manage stock in the two different types of chips.